1. Field of the Invention
The present invention relates generally to a precise and programmable duty cycle generator, and more particularly pertains to a precise and programmable duty cycle generator which enhances the operational frequency and precision over which the programmable duty cycle generator can operate.
Almost all ICs require a clock signal to accomplish their operations and be synchronous with other related components. The frequency of this clock determines the performance of the IC. As sub-micron technologies allow designs to operate at higher frequencies, design techniques must also provide for increasing their performance. An adjustable duty cycle clock circuit provides designers with flexibility in their designs, allowing them to meet high-performance and low-power goals. In addition to this flexibility, a programmable duty cycle adjuster provides robustness to the design. After fabrication, if the process was not modeled accurately, the duty cycle can be adjusted through the IC bus, fuses, or primary pins on the IC to operate the IC at the highest possible clock rate.
A prior disclosure, filed as U.S. patent application Ser. No. 10/020,528, on even date herewith, and titled, xe2x80x9cA Precise And Programma Duty Cycle Generatorxe2x80x9d, is hereby expressly incorporated by reference herein and describes a circuit to generate/create a user definable duty cycle with precision from an input signal having any duty cycle, and is described with reference to FIGS. 1-4 herein. As explained in that disclosure, for a fixed number of delay block stages the range of duty cycle selection is inversely proportional to the frequency of the signal at CLKIN. Pursuant to the present invention, this frequency range limitation can be alleviated by designing the VCDCG with a broad number of delay taps in conjunction with multiple tap points and multiplexing them at the output.
2. Discussion of the Prior Art
The idea of providing a circuit for duty cycle correction isn""t new. The prior art has circuits which correct an incoming signal""s duty cycle to a fixed value, typically 50xe2x80x9450. The present invention differs from the prior art by allowing the output corrected signal to be programmable to any value duty cycle with precision.
U.S. Pat. No. 4,881,041 discloses a circuit to correct an incoming signal""s duty cycle to a 50/50 duty cycle and is limited to a 50/50 duty cycle correction with no provision for any other duty cycle, and the circuit is completely different from the present invention. U.S. Pat. No. 5,157,277 discloses a circuit to convert a sine wave input clock signal at a 50/50 duty cycle into a square wave signal with a variable duty cycle. The conversion circuit is limited to sine wave inputs, and is significantly different from the present invention which addresses square wave signals.
Accordingly, it is a primary object of the present invention to provide an enhanced operational frequency for a precise programmable duty cycle generator which enhances the operational frequency and precision over which a programmable duty cycle generator can operate.